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• X. Wen, Chapter 3: Test Generation, pp. 51-71, Chapter 5: Logic Built-In Self-Test, pp. 94-114, Tsinghua University Press, Jun. 2024.

• Harry H. Chen, X. Wen, and W.-T. Cheng, Chapter 1: Prerequests on Fault Diagnosis, pp. 1-24, Springer Cham, Mar. 2023.

• X. Wen and I. Shimizu, Chapter 3: Product Classification, Introduction to Semiconductor Circuits, pp. 86-115, pp. 156-178, NIKKEI BP, Tokyo, Dec. 2020aaaaiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii iiiiiiiiiiiiiciiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii

• X. Wen, Chapter 1 (Partial): Designing LSI Circuits, Understanding by Measuring Semiconductor Circuits -Applications-, pp. 60-68, pp. 75-90, NIKKEI BP, Tokyo, May 2019.

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• X. Wen, H. Hatayama, et al., Chapter 3: Product Classification, Questions and Answers for Introduction to Semiconductor Circuits, pp. 81-126, NIKKEI BP, Tokyo, Dec. 2014.
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• X. Lin, X. Wen, and D. Xiang, Chapter 9: Low-Power Testing for 2D/3D Devices and Systems, Design of 3D Integrated Circuits and Systems, pp. 235-277, CRC Press, Boca Raton, Nov. 2014.

• X. Wen and H. Hatayama, Chapter 3: Product Classification, Introduction to Semiconductor Circuits, pp. 83-113, pp. 152-172, NIKKEI BP, Tokyo, May 2013.

• X. Wen and Y. Zorian, Part IV Circuit Testing, Chapter 20: Low-Power Testing for Low-Power LSI Circuits, Advanced Circuits for Emerging Technologies, pp. 511-528, John Wiley & Sons, New Jersey, June 2012.

• X. Wen and S. Wang, Chapter 3: Low-Power Test Generation, Power-Aware Testing and Test Strategies for Low Power Devices, pp. 65-115, Springer, New York, Nov. 2009.

• L.-T. Wang, X. Wen, and S. Wu, Chapter 7: Test Synthesis, Electronic Design Automation: Synthesis, Verification, and Test, pp. 405-448, Morgan Kaufmann, San Francisco, Oct. 2008.

• P. Girard, X. Wen, and N. A. Touba, Chapter 7: Low-Power Testing, System-on-Chip Test Architectures: Nanometer Design for Testability, pp. 307-350, Morgan Kaufmann, San Francisco, Nov. 2007.

• L.-T. Wang, X. Wen, and K. S. Abdel-Hafez, Chapter 2: Design for Testability, VLSI Test Principles and Architectures: Design for Testability, pp. 37-103, Morgan Kaufmann, San Francisco, July 2006.