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Built-In Self-Test
  1. L. Yu, J. Hung, B. Sheu, B. Huynh, L. Nguyen, S. Wu, L.-T. Wang, and X. Wen, "Hybrid Memory Built-In Self-Test Architecture for Multi-Port Static RAMs," Proc. of IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 331-339, Kyoto, Japan, Oct. 2010.
  2. S. Wu, L.-T. Wang, L. Yu, H. Furukawa, X. Wen, W.-B. Jone, N. A. Touba, F. Zhao, J. Liu, H.-J. Chao, F. Li, and Z. Jiang, "Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains," Proc. of IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 358-366, Kyoto, Japan, Oct. 2010.
  3. L.-T. Wang, X. Wen, S. Wu, H. Furukawa, H.-J. Chao, B. Sheu, J. Guo, and W.-B. Jone, "Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 2, pp. 299-312, Feb. 2010.
  4. S. Wu, H. Furukawa, B. Sheu, L.-T. Wang, H.-J. Chao, L. Yu, X. Wen, and M. Murakami, "Practical Challenges in Logic BIST Implementation: Case Studies," Proc. of IEEE Asian Test Symp., p. 265, Saporro, Japan, Nov. 2008.
  5. L.-T. Wang, X. Wen, B. Hsu, S. Wu, and J. Guo, "At-Speed Logic BIST Architecture for Multi-Clock Designs," Proc. of IEEE Int'l Conf. on Computer Design, pp. 475-478, San Jose, USA, Oct. 2005.
  6. B. Cheon, E. Lee, L.-T. Wang, X. Wen, P. Hsu, J. Cho, J. Park, H. Chao, S. Wu, "At-Speed Logic BIST for IP Cores," Proc. of Design Automation, and Test in Europe, pp. 860-861, Munich, Germany, Mar. 2005.
  7. X. Wen and H. Wang, "A Flexible Logic BIST Scheme and Its Application to SoC Designs," Proc. of IEEE Asian Test Symp., p. 463, Kyoto, Japan, Nov. 2001.
  8. H. Yokoyama, H. Tamamoto, and X. Wen, "Built-In Random Testing for Dual-Port RAMs," Proc. of IEEE Int’l Workshop on Memory Technology, Design and Testing, pp. 2-6, San Jose, USA, Aug. 1994.