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Test Generation
  1. N.A. Zakaria, M.Z Khalid, and X. Wen, "ATPG Enhancement Technology," Proc. of IEEE Workshop on RTL and High Level Testing, Paper IV.5.S, Yilan, Taiwan, Nov. 2013.
  2. N.A. Zakaria, W.Z.W. Hasan, I.A. Halin, R.M. Sidek, and X. Wen, "Fault Detection with Optimum March Test Algorithm," Journal of Theoretical and Applied Information Technology, Vol. 47, No. 1, pp. 18-27, Jan. 2013.
  3. K. Miyase, S. Kajihara, and X. Wen, "Estimation of the Amount of Don't-Care Bits in Test Vectors," Proc. of IEEE Workshop on RTL and High Level Testing, Paper 2.3, Niigata, Japan, Nov. 2012.
  4. S. Wu, L.-T. Wang, X. Wen, Z. Jiang, W.-B. Jone, M. S. Hsiao, L. Tan, Y. Zhang, C.-M. Li, and J.-L. Huang, "Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains," ACM Trans. on Design Automation of Electronic Systems, Vol. 17, Iss. 4, Article No. 48, Oct. 2012.
  5. N.A. Zakaria, W.Z.W. Hasan, I.A. Halin, R.M. Sidek, and X. Wen, "Fault Detection with Optimum March Test Algorithm," Proc. of IEEE Int'l Conf. on Intelligent Systems, Modeling and Simulation, Paper S8, Sabah, Malaysia, Feb. 2012.
  6. N.A. Zakaria, W.Z.W. Hasan, I.A. Halin, R.M. Sidek, and X. Wen, "Testing Static Single Cell Faults Using Static and Dynamic Data Background," Proc. of IEEE Student Conference on Research and Development, pp. 1-6, Cyberjaya, Malaysia, Dec. 2011.
  7. K. Miyase, F. Wu, L. Dilillo, A. Bosio, P. Girard, X. Wen, and S. Kajihara, "X-Identification of Transition Delay Fault Tests for Launch-off Shift Scheme," Proc. of IEEE Workshop on RTL and High Level Testing, pp. 125-129, Shanghai, China, Dec. 2010.
  8. N.A. Zakaria, E. V. Bautista, S. M. Jusoh, W. F. Lee, and X. Wen, "Case Studies on Transition Fault Test Generation for At-Speed Scan Testing," Proc. of IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 180-188, Kyoto, Japan, Oct. 2010.
  9. S. Kajihara, M. Matsuzono, H. Yamaguchi, Y. Sato, K. Miyase, and X. Wen, "On Test Pattern Compaction with Multi-Cycle and Multi-Observation Scan Test," Proc. of the 10th Int'l Symp. on Communications and Information Technologies, pp. 723-726, Tokyo, Japan, Oct. 2010.
  10. S. Oku, S. Kajihara, Y. Sato, K. Miyase, and X. Wen, "On Delay Test Quality for Test Cubes," IPSJ Trans. on System LSI Design Methodology, Vol. 3, pp. 283-291, Aug. 2010.
  11. M. Noda, S. Kajihara, Y. Sato, K. Miyase, X. Wen, and Y. Miura, "On Estimation of NBTI-Induced Delay Degradation," Proc. of IEEE European Test Symp., pp. 107-111, Prague, Czech, May 2010.
  12. M. Noda, S. Kajihara, Y. Sato, K. Miyase, X. Wen, and Y. Miura, "A Path Selection Method for Delay Test Targeting Transistor Aging," Digest of the 1st IEEE Int'l Workshop on Reliability Aware System Design and Test, pp. 57-61, Bangalore, India, Jan. 2010.
  13. S. Kajihara, S. Morishima, M. Yamamoto, X. Wen, M. Fukunaga, K. Hatayama, and T. Aikyo, "Estimation of Delay Test Quality and Its Application to Test Generation," IPSJ Trans. on System LSI Design Methodology, Vol. 1, pp. 104-115, Aug. 2008.
  14. S. Wu, L.-T. Wang, Z. Jiang, J. Soong, B. Sheu, X. Wen, M. S. Hsiao, C.-M. Li, J.-L. Huang, and R. Apte, "On Optimizing Pattern Count and ATPG Time Using A Hybrid Single-Capture Scheme for Testing Scan Designs," Proc. of IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 143-151, Cambridge, MA, USA, Oct. 2008.
  15. K. Miyase, K. Terashima, X. Wen, S. Kajihara, and S. M Reddy, "On Detection of Bridge Defects with Stuck-At Tests," IEICE Trans. on Inf. & Syst., Vol. E91-D, No. 3, pp. 683-689, Mar. 2008.
  16. S. Kajihara, S. Morishima, M. Yamamoto, X. Wen, M. Fukunaga, K. Hatayama, and T. Aikyo, "Estimation of Delay Test Quality and Its Application to Test Generation," Proc. of IEEE/ACM Int'l Conf. on Computer-Aided Design, pp. 413-417, San Jose, USA, Nov. 2007.
  17. K. Miyase, X. Wen, S. Kajihara, M. Yamamoto, H. Furukawa, "A Method for Improving the Bridging Defect Coverage of a Transition Delay Test Set," Proc. of IEEE Int'l Workshop on Defect Based Testing, pp. 51-56, Santa Clara, USA, Oct. 2007.
  18. S. Kajihara, S. Morishima, A. Takuma, X. Wen, T. Maeda, S. Hamada, and Y. Sato, "A Framework of High-quality Transition Fault ATPG for Scan Circuits," Proc. of IEEE Int'l. Test Conf., Paper 2.1, Santa Clara, USA, Oct. 2006.
  19. M. Fukunaga, S. Kajihara, X. Wen, T. Maeda, S. Hamada, and Y. Sato, "A Dynamic Test Compaction Procedure for High-Quality Path Delay Testing," Proc. of IEEE/ACM Asian and South Pacific Design Automation Conf., pp. 348-353, Yokohama, Japan, Jan. 2006.
  20. K. Miyase, K. Terashima, S. Kajihara, X. Wen, and S. M. Reddy, "On Improving Defect Coverage of Stuck-At Fault Tests," Proc. of IEEE Asian Test Symp., pp. 216-221, Calcutta, India, Dec. 2005.
  21. S. Kajihara, M. Fukunaga, X. Wen, T. Maeda, S. Hamada, and Y. Sato, "Path Delay Test Compaction with Process Variation Tolerance," Proc. of IEEE/ACM Design Automation Conf., pp. 845-850, Anaheim, USA, June 2005.
  22. K. Miyase, S. Nagayama, S. Kajihara, X. Wen, and S. M. Reddy, "On the Extraction of a Minimum Cube to Justify Signal Line Values," Proc. of Informal Digest of IEEE European Test Symp., pp. 79-84, Tallinn, Estonia, May 2005.
  23. K. Miyase, S. Nagayama, S. Kajihara, X. Wen, and S. M. Reddy, "On Extraction of a Cube with the Minimum Number of Literals from a Given Input Vector," Proc. of IEEE Workshop on RTL and High Level Testing, pp. 71-76, Osaka, Japan, Nov. 2004.