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Yield Improvement
- T. Ni, W. Rui, M. Niu, Y. Li, C. Zhou, and X. Wen, "A Novel Approach
to Reducing Testing Costs and Minimizing Defect Escapes Using Neighborhood
Range and Shapley Values," ACM Trans. on Design Automation of Electronic Systems. (Accepted).
- H. Xu, T. Wang, Z. Zhao, R. Ma, X. Wen, and H. Liang, "Hi-ILT: A Hybrid
End-to-End Framework of Lightweight Hierarchical VAE and Physics-Guided
ILT for Inverse Lithography Technology," Optics and Lasers in Engineering, Vol. 200, 109621, May 2026.
- T. Ni, W. Jiang, H. Liang, X. Wen, and M. Nie, "Incremental Learning
Strategies for Improved Detection of Unknown Defects in Wafer Maps with
Limited Samples," Computers in Industry, Vol. 175, 104432, Feb. 2026.
- W. Zhan, Y. Zhou, J. Zheng, and X. Wen, "A Method for Integrated Circuit
Trimming Focused on Seperation of Trim Codes," Microelectronics Reliability, Vol. 174, 115889, Nov. 2025.
- Z. Guo, A. Yan, Z. Huang, J. Cui, B. Roh, G. Liu, P. Girard, and X. Wen,
"Graph-Based Multi-Task Transfer Learning for Fault Ditection and
Diagnosis of Few-Shot Analog Circuits," The IEEE Internet of Things Journal, Vol. 12, No. 12, pp. 21264-21279, Jun 2025.
- T. Ni, W. Jiang, H. Liang, X. Wen, and M. Nie, "Segmentation-Enhanced
Overlapped Defect Identification for Multi-Patterns Wafer Maps," IEEE Trans. on Instrumentation & Measurement, Vol. 74, pp. 1-11, May 2025.
- M. Niu, S. Zhu, A. Yan, Z. Chen, X. Wen, and T. Ni, "Efficient Modulated
State Space Model for Mixed-Type Wafer Defect Pattern Recognition," Proc. of IEEE Design, Automation and Test in Europe, Paper TS16.4, Lyon, France, Mar. 2025.
- W. Zhan, Y. Zhou J. Zheng, X. Cai, Q. Zhang, and X. Wen, "A Method
for Grading Failure Rates within the Dynamic Effective Space of Integarted
Circuits after Testing," Applied Sciences, 2025, 15, 2009.
- X. Wen, "LSI Testing: A Core Technology to A Successful LSI Industry,"
Proc. of IEEE Int'l Conf. on ASIC, Paper P0065, Kunming, China, Oct. 2021.
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