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US Patent Applications

Details can be found at here by typing "IN/Xiaoqing AND IN/Wen ANDNOT IC/Beijing" into the Refine Search field.

1 20160131707 MULTIPLE-CAPTURE DFT METHOD FOR DETECTING OR LOCATING CROSSING CLOCK-DOMAIN FAULTS DURING SELF-TEST OR SCAN-TEST
2 20150338465 MULTIPLE-CAPTURE DFT SYSTEM FOR DETECTING OR LOCATING CROSSING CLOCK-DOMAIN FAULTS DURING SCAN-TEST
3 20150316616 MULTIPLE-CAPTURE DFT SYSTEM FOR DETECTING OR LOCATING CROSSING CLOCK-DOMAIN FAULTS DURING SCAN-TEST
4 20130305200 COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL
5 20120246604 COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL
6 20110209024 GENERATION DEVICE, CLASSIFICATION METHOD, GENERATION METHOD, AND PROGRAM
7 20110197171 COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL
8 20110140734 GENERATING DEVICE, GENERATING METHOD, AND PROGRAM
9 20100218063 DON'T-CARE-BIT IDENTIFICATION METHOD AND DON'T-CARE-BIT IDENTIFICATION PROGRAM
10 20100218062 Method and Apparatus for Unifying Self-Test with Scan-Test During Prototype Debug and Production Test
11 20100205491 LOGIC VALUE DETERMINATION METHOD AND LOGIC VALUE DETERMINATION PROGRAM
12 20100095179 TEST PATTERN GENERATION METHOD FOR AVOIDING FALSE TESTING IN TWO-PATTERN TESTING FOR SEMICONDUCTOR INTEGRATED CIRCUIT
13 20100064191 DIAGNOSTIC DEVICE, DIAGNOSTIC METHOD, PROGRAM, AND RECORDING MEDIUM
14 20090319842 GENERATING DEVICE, GENERATING METHOD, PROGRAM AND RECORDING MEDIUM
15 20090259898 Test vector generating method and test vector generating program of semiconductor logic circuit device
16 20090235132 METHOD AND APPARATUS FOR BROADCASTING SCAN PATTERNS IN A SCAN-BASED INTEGRATED CIRCUIT
17 20090132880 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
18 20090083593 Test Method and Test Program of Semiconductor Logic Circuit Device
19 20090070646 Multiple-Capture DFT system for scan-based integrated circuits
20 20090037786 Method and apparatus for unifying self-test with scan-test during prototype debug and production test
21 20090019327 GENERATING DEVICE, GENERATING METHOD, PROGRAM AND RECORDING MEDIUM
22 20080276141 Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
23 20080235543 CONVERSION DEVICE, CONVERSION METHOD, PROGRAM, AND RECORDING MEDIUM
24 20080134107 Computer-aided design system to automate scan synthesis at register-transfer level
25 20070255988 Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults
26 20070168803 Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
27 20060156122 Mask network design for scan-based integrated circuits
28 20050262409 Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits
29 20050235186 Multiple-capture DFT system for scan-based integrated circuits
30 20050229123 Computer-aided design system to automate scan synthesis at register-transfer level
31 20050060625 Mask network design for scan-based integrated circuits
32 20050055617 Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit
33 20040268181 Method and apparatus for unifying self-test with scan-test during prototype debug and production test
34 20040237015 Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits
35 20040153926 Method and apparatus for testing asynchronous set/reset faults in a scan-based integrated circuit
36 20030154433 Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
37 20030023941 Computer-aided design system to automate scan synthesis at register-transfer level
38 20020194558 Method and system to optimize test cost and disable defects for scan and BIST memories
39 20020184560 Multiple-capture DFT system for scan-based integrated circuits
40 20020138801 Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
41 20020120896 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test