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US Issued Patents

Details can be found at here by typing "IN/Xiaoqing AND IN/Wen ANDNOT IC/Beijing" for into the Refine Search field.

1 9,696,377 Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
2 9,678,156 Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test
3 9,316,688 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test
4 9,274,168 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test
5 9,091,730 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test
6 8,775,985 Computer-aided design system to automate scan synthesis at register-transfer level
7 8,589,751 Don't-care-bit identification method and don't-care-bit identification program
8 8,543,950 Computer-aided design system to automate scan synthesis at register-transfer level
9 8,453,023 Target logic value determination method for unspecified bit in test vector for combinational circuit and non-transitory computer-readable medium
10 8,429,472 Generating device, generating method, and program
11 8,219,945 Computer-aided design system to automate scan synthesis at register-transfer level
12 8,117,513 Test method and test program of semiconductor logic circuit device
13 8,001,437 Test pattern generation method for avoiding false testing in two-pattern testing for semiconductor integrated circuit
14 7,979,765 Generating device, generating method, program and recording medium
15 7,971,118 Conversion device, conversion method, program, and recording medium
16 7,962,822 Generating device, generating method, program and recording medium
17 7,945,830 Method and apparatus for unifying self-test with scan-test during prototype debug and production test
18 7,913,144 Diagnostic device, diagnostic method, program, and recording medium
19 7,904,857 Computer-aided design system to automate scan synthesis at register-transfer level
20 7,904,773 Multiple-capture DFT system for scan-based integrated circuits
21 7,779,323 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
22 7,779,322 Compacting test responses using X-driven compactor
23 7,747,920 Method and apparatus for unifying self-test with scan-test during prototype debug and production test
24 7,743,306 Test vector generating method and test vector generating program of semiconductor logic circuit device
25 7,735,049 Mask network design for scan-based integrated circuits
26 7,721,173 Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
27 7,552,373 Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
28 7,512,851 Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit
29 7,478,295 Method and apparatus of fault diagnosis for integrated logic circuits
30 7,451,371 Multiple-capture DFT system for scan-based integrated circuits
31 7,444,567 Method and apparatus for unifying self-test with scan-test during prototype debug and production test
32 7,434,126 Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults
33 7,412,672 Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
34 7,331,032 Computer-aided design system to automate scan synthesis at register-transfer level
35 7,284,175 Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
36 7,260,756 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test
37 7,191,373 Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
38 7,124,342 Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits
39 7,058,869 Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits
40 7,032,148 Mask network design for scan-based integrated circuits
41 7,007,213 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
42 6,957,403 Computer-aided design system to automate scan synthesis at register-transfer level
43 6,954,887 Multiple-capture DFT system for scan-based integrated circuits