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Invited Talks
  1. "Integrated Circuit Industry and Integrated Circuit Testing Technology", School of Microelectronics, Southeat University, Nanjing, China, Oct. 29, 2024.
  2. "LSI Testing: A Core Technology for a Successful Semiconductor Industry", 集積回路与智能光電検討会, Yinchuan, China, May 7, 2024.
  3. "Assessing the Power-Awareness of VLSI Testing", Conference of Science and Technology for Integrated Circuits, Mar. 17, 2024. Virtual Event
  4. "半導体の光と影と癖　〜半導体グルーバル大競争への複層的視点〜",プロジェクトマネジメント学会九州支部２０周年記念シンポジウム, Nov. 9, 2023.
  5. Power-Aware Testing for Low-Power LSI Circuits", China Semiconductor Technology International Comference, Symposium VI, Jun. 26, 2023. Virtual Event
  6. "The Light, Shadow, and Habit of Semiconductor Circuits", Special Seminar of the Association of Chinese Professors in Japan, Nov. 27, 2022. Virtual Event
  7. "Power-Aware IC Testing: Present and Future", The 1st CCF Chip Conference, Nanjing, China, Jul. 30, 2022. Hybrid Event
  8. "LSI Testing: A Core Technology to A Successful LSI Industry", The IEEE International Conference on ASIC, Kumming, China, Oct. 29, 2021. Virtual Event
  9. "Power-Aware Testing for Low-Power LSI Circuits", The 9th IEEE International Symposium on Next-Generation Electronics, Changsha, China, Jul. 10, 2021. Virtual Event
  10. "LSI Test: from Research to Business", The 18th China Fault Tolerant Computing Conference, Beijing, China, Aug. 15, 2019.
  11. "Power-Aware Testing of Low-Power VLSI Circuits", The 15th IEEE International Conference on Electron Devices and Solid-State Circuits, Xi'an, China, Jun. 13, 2019.
  12. "Power-Aware Testing for Low-Power LSI Circuits", Beijing University of Technology, Beijing, China, Dec. 28, 2018.
  13. "All about ICs: From Technology Trends to Career Choices", School of Software, Tsinghua University, Beijing, China, Dec. 26, 2018.
  14. "Power-Aware LSI Testing: Challenges and Strategies", Beijing University of Aeronautics and Astronautics, Beijing, China, Mar. 29, 2018.
  15. "Power-Aware Testing for Low-Power VLSI Circuits", School of Software, Tsinghua University, Beijing, China, Dec. 29, 2017.
  16. "All abour ICs: From Technology Trends to Career Choices", School of Computer Science and Technology, Anhui University, Xuancheng, China, Mar. 10, 2017.
  17. "All abour ICs: From Technology Trends to Career Choices", Xuancheng Campus, Hefei University of Technology, Xuancheng, China, Mar. 8, 2017.
  18. "All abour ICs: From Technology Trends to Career Choices", School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei, China, Mar. 7, 2017.
  19. "Power-Aware Testing For Low-Power VLSI Circuits", The 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, Hangzhou, China, Oct. 26, 2016.
  20. "IC: Technical Trends and Career Development", Nantong University, Nantong, China, Oct. 24, 2016.
  21. "Power Supply Noise and Its Reduction in At-Speed Scan Testing", The IEEE 11th International Conference on ASIC, Chengdu, China, Nov. 5, 2015.
  22. "From Low-Power Test to Power-Safe Test", Duke University, Durham, USA, Oct. 17, 2014.
  23. "From Low-Power Test to Power-Safe Test", Tsinghua University, Beijing, China, Oct. 10, 2014.
  24. "From Low-Power Test to Power-Safe Test", Hefei University of Technology, Hefei, China, Sep. 23, 2014.
  25. "Power-Aware Testing: The Next Stage", University of Stuttgart, Stuttgart, Germany, May 21, 2014.
  26. "Low-Power LSI Testing", The 13th International Workshop on Microelectronics Assembling and Packaging, Fukuoka, Japan, Nov. 7, 2013.
  27. "Power-Aware Testing: The Next Stage", National Sun Yat-Sen University, Kaohsiung, Taiwan, Sep. 26, 2013.
  28. "Power-Aware Testing: The Next Stage", National Chun Hsing University, Taichung, Taiwan, Sep. 17, 2013.
  29. "Power-Aware Testing: The Next Stage", Hefei University of Technology, Hefei, China, Jun. 26, 2013.
  30. "Towards the Next-Generation Power-Aware Testing Technologies", CMOS Emerging Technologies Conference, Vancouver, Canada, Jul. 19, 2012.
  31. "半導体集積回路の同歩留り化プラットフォームの研究開発", 福岡県先端半導体意見交換会, Apr. 9, 2012.
  32. "Power-Aware Testing for Low-Power VLSI Circuits", State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Science, Beijing, China, Mar. 29, 2012.
  33. "Power-Aware Testing for Low-Power VLSI Circuits", School of Software, Tsinghua University, Beijing, China, Mar. 29, 2012.
  34. "Power-Aware Testing for Low-Power VLSI Circuits", ECE Seminar, University of Connecticut, Storrs, USA, Dec. 16, 2011.
  35. "Low-Power Testing for Low-Power Devices", Hong Kong Chinese University, Hong Kong, China, Oct. 6, 2011.
  36. "Low-Power Testing for Low-Power Devices", AMD Tech Forum, Shanghai, China, Jan. 24, 2011.
  37. "Power-Aware Test for Low-Power Devices", International Workshop on Microelectronics Assembling and Packaging, Fukuoka, Japan, Nov. 18, 2010.
  38. "Low-Aware Test for Low-Power Devices", IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Kyoto, Japan, Oct. 7, 2010.
  39. "Power-Aware Test for Low-Power LSI Circuits", CMOS Emerging Technologies Conference, Whistler, Canada, May 19, 2010.
  40. "Challenges and Chances in Deep-Submicron LSI Testing", Academic Forum on Computer Science and Technology, Shanghai University, Shanghai, China, Mar. 20, 2010.
  41. "省電力志向テスト技術(Power-Aware Testing) の現状と課題", 第4回四国シリコンテスト技術研究会, 平成22年2月5日.
  42. "From Artillery Fire to Sniper Fire: A Paradigm Shift in Test Power Reduction", Elevator Talk Session, IEEE International Test Conference, Austin, USA, Nov. 5, 2009.
  43. "Low-Power Test Generation for Reducing Yield Loss Risk in At-Speed Scan Testing", Special Seminar at University of Wisconsin - Madison, Madison, USA, Oct. 30, 2009.
  44. "VLSIの低消費電力テスト技術", 半導体テスト技術交流会, 平成21年2月13日.
  45. "低消費電力テスト: 現状と展望", アドバンテスト展テクニカルセミナー, 平成20年6月4日.
  46. "Challenges and Chances in Deep-Submicron LSI Testing", Electrical and Computer Engineering, University of Connecticut, Storres, USA, Apr. 25, 2008.
  47. "Test Strategies for Low Power Devices (Power Issues during Test)", Hot-Topic Session, Design, Automation, and Test in Europe, Germany, Mar. 12, 2008. (Report)
  48. "SIAT：Signal-Integrity-Aware Testing", SEMI テクノロジーシンポジウム, 平成19年12月6日.
  49. "LSIテスト技術の開発動向について", 平成1９年度知的財産セミナー, 平成19年11月15日.
  50. "テスト技術の概論と最新動向", 平成19年度大分県LSIクラスター推進会議総会, 平成19年7月23日.
  51. "SIAT：Signal-Integrity-Aware Testingを目指して", JEITA: STRJ-WG2, 平成18年10月5日.
  52. "集積回路の高信頼化技術", 九州工業大学技術交流会（三木会）, 平成18年5月18日.
  53. "集積回路のテスト技術の研究開発", 第１9回e-ZUKAトライバレー産学官交流研究会, 平成18年4月12日.
  54. "Low-Capture-Power Test Generation for Scan-Based At-Speed Testing", Computer Engineering Seminar, University of Wisconsin - Madison, Madison, USA, Oct. 30, 2005.
  55. "ディジタルＬＳＩのテスト技術の最新動向", ウエハテストビジネス研究会, 平成17年6月28日.
  56. "LSIテスト: 現状と動向", 福岡県産業・科学技術振興財団VLSIテスト技術研究会, 平成17年3月23日.
  57. "A Method for Low-Capture-Power At-Speed Test Generation", School of Software Engineering, Tsinghua University, Beijing, China, Jan. 21, 2005.
  58. "ＬＳＩテストとテスト容易化設計　〜現状と動向〜", 平成16年度第4回大分県半導体関連企業ビジネスチャンス研究会, 平成16年12月15日.
  59. "On Low-Capture-Power Test Generation for Scan Testing", School of Software Engineering, Tsinghua University, Beijing, China, Oct. 6, 2004.
  60. "On Low-Capture-Power Test Generation for Scan Testing", Institute of Computing Technology, Beijing, China, Oct. 4, 2004.
  61. "At-Speed Logic BIST for Multi-Clock Multi-frequency Designs", Center for Reliable Computing, Stanford University, Beijing, China, Jun. 19, 2002.