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Reliability

  1. H. Xu, J. Li, R. Ma, H. Liang, C. Liu, S. Wang, and X. Wen, "A Low Area-Overhad and Low DElay Triple-Node-Upset Self-Recoverable Design Based on Stacked Transistors," IEEE Trans. on Device and Material Reliability. (Early Access)
  2. Z. Huang, L. Sun, X. Wang, H. Liang, L. Lu, A. Yan, J. Pan, and X. Wen, "NEST: A Quadruple-Node Upset Recovery Latch Design and Algorithm-Based Recovery Optimization," IEEE Trans. on Aerospace and Electronics Systems. (Early Access)
  3. A. Yan, Z. Li, Z. Huang, T. Ni, J. Cui, P. Girard, and X. Wen, "MURLAV: A Multiple-Node-Upset Recovery Latch and Algoritm-based Verification Method," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems. (Early Access)
  4. A. Yan, Y. Chen, T. Ni, Z. Huang, J. Cui, P. Girard, and X. Wen, "FeMPIM: A FeFET-based Multifunctional Processing-in-Memory Cell," IEEE Trans. on Circuits and Systems II: Express Briefs, Vol. 71, Iss. 4, pp. 2299-2303, Apr. 2024.
  5. A. Yan, L. Wang, J. Cui, Z. Huang, T. Ni, P. Girard, and X. Wen, "Non-Volatile Latch Dseigns with Node-Upset Tolerance and Recovery using Magnetic Tunnel Junctions and CMOS," IEEE Trans. on VLSI, Vol. 32, Iss. 1, pp. 116-127, Jan. 2024.
  6. K. Katoh, T. Nakura, X. Wen, and H. Kobayashi, "A Fine On-Chip Online Delay Measurement Using a MUX Chain for Failure Prediction and Analysis," Proc. of the 7th Int`l Conf. on Technology and Social Science, Paper IPS-02-05, Dec. 2023.
  7. A. Yan, X. Li, Z. Zhou, Z. Huang, T. Ni , and X. Wen, "Advanced DICE Based Triple-Node-Upset Recovery Latch with Optimized Overhead for Space Applications," Proc. of IEEE Asian Test Symp., Paper 2A-1, Beijing, China, Oct. 2023.
  8. A. Yan, L. Wang, T. Ni, J. Cui, Z. Huang, and X. Wen, "A Non-Volatile and Double-Node-Upset Recoverable Latch Based on Magnetic Junctions and CMOS," Proc. of IEEE Asian Test Symp., Paper 2A-2, Beijing, China, Oct. 2023.
  9. A. Yan, Y. Chen, Z. Huang, J. Cui, and X. Wen, "A High-Performance and P-Type FeFET-Based Non-Volatile Latch," Proc. of IEEE Asian Test Symp., Paper 2B-3, Beijing, China, Oct. 2023.
  10. A. Yan, F. Xia, T. Ni, J. Cui, Z. Huang, P. Girard, and X. Wen, "A Low Overhead and Double-Node-Upset Self-Recoverable Latch," Proc. of the 7th Int'l Test Conf. in Asia, Paper 3B-1, Shimane, Japan, Sep. 2023.
  11. A. Yan, C. Zhou, S. Wei, J. Cui, Z. Huang, P. Girard, and X. Wen, "Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness," Proc. of the 7th Int'l Test Conf. in Asia, Paper 3B-2, Shimane, Japan, Sep. 2023.
  12. A. Yan, J. Xiang, Y. Chang, Z. Huang, J. Cui, P. Girard, and X. Wen, "Design of a Highly Reliable and Low-Power SRAM with Double-Node-Upset Recovery for Safety-Critical Applications," Proc. of the 7th Int'l Test Conf. in Asia, Paper 4B-2, Shimane, Japan, Sep. 2023.
  13. A. Yan, J. Xiang, Z. Huang, T. Ni, J. Cui, P. Girard, and X. Wen, "Two Sextuple Cross-Coupled SRAM Cells with Double-Node-Upset Protection and Cost Optimization for Aerospace Applications," Microelectronics Journal, Vol. 139, 105908, Sep. 2023.
  14. A. Yan, X. Li, , T. Ni, Z. Huang, and X. Wen, "A Robust and High-Performance Flip-Flop with Complete Soft-Error Recovery," Proc. of the 10th Int'l Conf. on Dependable systems and Their Applications, Paper IV-B-5, Tokyo, Japan, Aug. 2023.
  15. A. Yan, Y. He, Z. Li, J. Cui, T. Ni, Z. Huang, P. Girard, and X. Wen, "A Highly Robust and Low Power Flip-Flop Cell with Complete Double-Node-Upset Tolerance for Aerospace Applications," IEEE Design & Test, Vol. 40, No. 4, pp. 34-41, Aug. 2023.
  16. A. Yan, Y. Chang, J. Li, Xiang. H, Lou. J. Cui, Z. Huang, T. Ni, and X. Wen, "Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications," Proc. of the 33rd Great Lake Symp. on VLSI, pp. 293-298, Knoxville, USA, Jun. 2023.
  17. A. Yan, S. Wei, J. Zhang, J. Cui, J. Song, Xiang, T. Ni, P. Girard, and X. Wen, "A Low Area and Low Dealy Latch Design with Complete Double-Node-Upset-Recovery For Aerospace Applications," Proc. of the 33rd Great Lake Symp. on VLSI, pp. 167-171, Knoxville, USA, Jun. 2023.
  18. A. Yan, Z. Li, J. Cui, Z. Huang, T. Ni, P. Girard, and X. Wen, "Designs of Two Quadruple-Node-Upset Self-Recoverable Latches fot Highly Robust Computing in Harsh Radiation Environments," Trans. on Aerospace and Electronics Systems, Vol. 59, No. 3, pp. 2885-2897, Jun. 2023.
  19. A. Yan, Z. Li, Z. Zhou, J. Cui, Z. Huang, T. Ni, P. Girard, and X. Wen, "LDAVPM: A Latch Design and Algorithm-based Verification Protected against Multiple-Node-Upsets in Harsh Radiation Environments," Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 42, No. 6, pp. 2069-2073, Jun. 2023.
  20. S. Holst, R. Ma, X. Wen, A. Yan, and H. Xu, "BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell," Poster at IEEE European Test Symp., Poster PS-7-1, Venice, Italy, May 2023.
  21. A. Yan, S. Wei, Z. Li, J. Cui, Z. Huang, P. Girard, and X. Wen, "Design of Low-Cost Approximate CMOS Full Adders," Proc. of the 56th IEEE Int'l Symp. on Circuits and Systems, Paper 1185, May 2023.
  22. T. Ni, Q. Peng, J. Bian, L. Yao, Z. Huang, A. Yan, and X. Wen, "MRCO: A Multi-Ring Convergence Oscillator-Based High-Efficiency True Random Number Generator," Proc. of Asian Hardware Oriented Security and Trust Symp., Paper 2.4, Singapore, Dec. 2022. (Best Paper)
  23. B. Lim, S. Holst, and X. Wen, "GPU-Accelerated Timing Simulation of Systolic-Array-Based Accelerators," Proc. of the 10th Int'l Symp. on Applied Engineering and Sciences, Paper -4-5, Kitakyushu, Japan, Dec. 2022.
  24. A. Yan, L. Ding, Z. Zhou, Z. Huang, J. Cui, P. Girard, and X. Wen, "A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage," Proc. of IEEE Asian Test Symp., Paper 1.1, Taichung, Taiwan, Nov. 2022.
  25. A. Yan, S. Wei, Y. Chen, Z. Fan, Z. Huang, J. Cui, P. Girard, and X. Wen, "A ReRAM-Based Non-Volatile and Radiation-Hardened Latch," Micromachines, Vol. 13, No. 11, 1802, Oct. 2022.
  26. A. Yan, K. Qian, T. Song, Z. Huang, T. Ni, Y. Chen, and X. Wen, "A Double-Node-Upset Completely Tolerant CMOS Latch Design with Extremely Low Cost for High-Performance Applications," Integration, the VLSI Journal, Vol. 86, pp. 22-29, Sep. 2022.
  27. A. Yan, S. Song, J. Zhang, J. Cui, Z. Huang, T. Ni, X. Wen, and P. Girard, "Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS," Proc. of IEEE Int'l Test Conf. in Asia, Paper A4-2, Taipei, Taiwan, Aug. 2022.
  28. A. Yan, S. Song, J. Zhang, J. Cui, Z. Huang, T. Ni, X. Wen, and P. Girard, "Design of A Novel Double-Node-Upset-Recovery Latch with Low Cost Based on C-elements," Post. at the 1st CCF Chip Conf., Nanjing, China, Jul. 2022.
  29. A. Yan, Z. Li, Q. Wang, J. Cui, T. Ni, Z. Huang, X. Wen, and P. Girard, "LDAVPM: A Latch Design with Algorithm-based Verification Protected against Multiple-Node-Upsets in Harsh Radiation Environments," Proc. of IEEE/ACM Design Automation Conf., San Francisco, USA, WIP Poster, Jul. 2022.
  30. A. Yan, S. Song, Y. Chen, J. Cui, Z. Huang, and X. Wen, "A Low-Cost and Robust Latch Protected against Triple Node Upsets in Nanoscale CMOS based on Source-Drain Cross-Coupled Inverters," Proc. of IEEE Int'l Conf. on Nanotechnology, Paper AB26-2, Palma de Malloca, Spain, Jul. 2022.
  31. A. Yan, J. Xiang, A. Cao, Z. He, J. Cui, T. Ni, Z. Huang, X. Wen, and P. Girard, "Quadruple and Sextuple Cross-Coupled SRAM Cell Designs with Optimized Overhead for Reliable Applications," Trans. on Device and Materials Reliability, Vol. 22, No. 2, pp. 282-295, Jun. 2022.
  32. A. Yan, Z. Zhou, S. Wei, J. Cui, Y. Zhou, T. Ni, P. Girard, and X. Wen, "A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology," Proc. of the 32nd Great Lake Symp. on VLSI, pp. 255-260, Irvine, USA, Jun. 2022.
  33. A. Yan, Z. He, J. Xiang, J. Cui, Y. Zhou, Z. Huang, P. Girard, and X. Wen, "Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications," Proc. of the 32nd Great Lake Symp. on VLSI, pp. 261-266, Irvine, USA, Jun. 2022.
  34. A. Yan, Y. Chen, S. Song, Z. Zhai, J. Cui, Z. Huang, P. Girard, and X. Wen, "Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications," Proc. of the 32nd Great Lake Symp. on VLSI, pp. 333-338, Irvine, USA, Jun. 2022.
  35. A. Yan, R. Liu, Z. Huang, P. Girard, and X. Wen, "Designs of Level-Sensitive T Flip-Flops and Polar Encoders Based on Two Novel XOR/XNOR Gates," MDPI Electronics 2022, Vol. 11, No. 10, 1658, May 2022.
  36. R. Ma, S. Holst, X. Wen, A. Yan, and H. Xu, "Evaluation and Test of Production Defects in Hardened Latches," IEICE Trans. on Inf. & Syst., Vol. E105-D, No. 5, pp. 996-1009, May 2022.
  37. A. Yan, K. Qian, J. Cui, N. Cui, Z. Huang, X. Wen, and P. Girard, "A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications," Proc. of IEEE VLSI Test Symp., Paper S4-2, San Diego, USA, Apr. 2022.
  38. A. Yan, Z. Li, S. Huang, Z. Zhai, X. Cheng, J. Cui, T. Ni, X. Wen, and P. Girard, "SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments," Proc. of IEEE Design, Automation and Test in Europe, Paper 21.2.5, Antwerp, Belgium, Mar. 2022.
  39. A. Yan, Z. Fan, L. Ding, J. Cui, Z. Huang, Q. Wang, H. Zheng, P. Girard, and X. Wen, "Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications," IEEE Tran. on Aerospace and Electronic Systems, Vol. 58, No. 1, pp. 517-529, Feb. 2022.
  40. Y. Yan, Z. Xu, X. Feng, J. Cui, Z. Chen, T. Ni, Z. Huang, P. Girard, and X. Wen, "Novel Quadruple-Node-Upset-Tolerant Latch Designs with Optimized Overhead for Reliable Computing in Harsh Radiation Environments," IEEE Trans. on Emerging Topics in Computing, Vol. 10, No. 1, pp 404-413, Jan.-Mar. 2022.
  41. A. Yan, Z. Fan, Z. Xu, J. Cui, X. Chen, Z. Huang, T. Ni, H. Bao, and X. Wen, "QRHIL: A QNU-Recoverable and HIS-Insensitive Latch Design for Space Applications in Harsh Radiation Environments," WIP Presentation at IEEE/ACM Design Automation Conf., San Francisco, USA, Dec. 2021.
  42. R. Ma, S. Holst, and X. Wen, "STAHL: A Novel Scan-Test-Aware Hardened Latch," Proc. of the 9th Int'l Symp. on Applied Engineering and Sciences, Paper CS23, Serdang, Malaysia, Dec. 2021.
  43. S. Holst, B. Lim, and X. Wen, "Functional Safety of AI Accelerators with Hardware Defects," Proc. of the 9th Int'l Symp. on Applied Engineering and Sciences, Paper CS08, Serdang, Malaysia, Dec. 2021.
  44. S. Holst, B. Lim, and X. Wen, "GPU-Accelerated Timing Simulation of Systolic Array Based AI Accelerators," Proc. of IEEE Asian Test Symp., Paper S7.2, Ehime, Japan, Nov. 2021. (Best Paper Award) (ATS 30th Anniversary Compendium Paper)
  45. A. Yan, Y. Chen, N. Cui, J. Song, T. Ni, Z. Huang, and X. Wen, "Triple-Node-Upset-Tolerant Latch Designs with Configurable SET-Pulse-Filterability for Safety-Critical Applications," Proc. of CCF Integrated Circuit Design and Automation Conf., pp. 1-12, Wuhan, China, Oct. 2021.
  46. A. Yan, K. Qian, T. Song, Z. Huang, T. Ni, Y. Chen, and X. Wen, "A Double-Node-Upset Completely Tolerant CMOS Latch Design with Extremely Low Cost," Proc. of CCF Integrated Circuit Design and Automation Conf., pp. 1-12, Wuhan, China, Oct. 2021.
  47. A. Yan, K. Qian, J. Cui, N. Cui, T. Ni, Z. Huang, and X. Wen, "A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch," Proc. of IEEE/ACM Symp. on Nanoscale Architectures, Paper 3.4, Virtual Event, Nov. 2021.
  48. A. Yan, Z. Zhai, L. Wang, J. Zhang, N. Cui, T. Ni, and X. Wen, "Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing," Proc. of IEEE Int'l Test Conf. in Asia, pp. 1-6, Shanghai, China, Aug. 2021.
  49. A. Yan, A. Cao, K. Qian, Z. He, L. Ding, Z. Fan, and X Wen, "A Reliable and Low-Cost Flip-Flop Hardened against Double-Node-Upsets," Proc. of IEEE Int'l Conf. on Dependable Systems and Their Applications, pp. 1-2, Yinchuan, China, Aug. 2021.
  50. A. Yan, A. Cao, Z. Xu, J. Cui, T. Ni, P. Girard, and X. Wen, "Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications," J. Electron Test, Vol. 37, pp. 489-502, Aug. 2021.
  51. A. Yan, A. Cao, Z. Fan, Z. Xu, T. Ni, P. Girard, and X. Wen, "A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments," Proc. of ACM Great Lakes Symp. on VLSI, pp. 1-6, Virtual Event, Jun. 2021.
  52. A. Yan, L. Ding, C. Shan, H. Cai, X. Chen, Z. Wei, Z. Huang, and X. Wen, "TPDICE and SIM Based 4-Node-Upset Completely Hardened Latch Design for Highly Robust Computing in Harsh Radiation," IEEE Int'l Symp. on Circuits and Systems, DOI: 10.1109/ISCAS51556.2021.9401453, Daegu, Korea, May 2021.
  53. A. Yan, Z. He, J. Zhou, J. Cui, T. Ni, Z. Huang, X. Wen, and P. Girard, "Dual-Modular-Redundancy and Dual-Level Error-Interception based Triple-Node-Upset Tolerant Latch Designs for Safety-Critical Applications," Microelectronics Journal, Vol. 111, 105034, May 2021.
  54. Q. Xu, J. Wang, H. Geng, S. Chen, and X. Wen, "Reliability-Driven Neuromorphic Computing Systems Design," Proc. of Design, Automation and Test in Europe, Paper 11.7.2, Grenoble, France, Feb. 2021.
  55. A. Yan, C. Lai, Y. Zhang, C. Liu, Z. Chen, Q. He, Z. Huang, and X. Wen, "Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS," IEEE Trans. on Emerging Topics in Computing, Vol. 9, No. 1, pp. 520-533, Jan.-Mar. 2021.
  56. A. Yan, Y. Chen, Y. Hu, J. Zhou, T. Ni, J. Cui, P. Girard, and X. Wen, "Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets," IEEE Trans. on Circuits and Systems I: Regular Papers, Vol. 67, No. 12, pp. 4684-4695, Dec. 2020.
  57. A. Yan, Y. Chen, J. Zhou, J. Cui, T. Ni, X. Wen, and P. Girard, "A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets," Proc. of IEEE Asian Test Symp., Paper A2-1, Penang, Malaysia, Nov. 2020. (ATS 30th Anniversary Compendium Paper)
  58. R. Ma, S. Holst, X Wen, A. Yan, and H. Xu, "A Novel High Performance Scan-Test-Aware Hardened Latch Design," Proc. of IEEE Workshop on RTL and High Level Testing, Paper S2.2, Penang, Malaysia, Nov. 2020.
  59. A. Yan, Z. Xu, Y. Ling, Ji.Cui, Z. Ying, P. Girard, and X. Wen, "Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications," Proc. of IEEE Int'l Symp. on Circuits & Systems, pp. 1-5, Seville, Spain, Oct. 2020.
  60. A. Yan, Y. Chen, Z. Xu, Z. Chen, J. Cui, Z. Huang, P. Girard, and X. Wen, "Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low Power and Low-Orbit Aerospace Applications," IEEE Trans. on Aerospace and Electronic Systems, Vol. 56, No. 5, pp. 3931-3940, Oct. 2020.
  61. Z. Dou, A. Yan, J. Zhou, Y. Hu, Y. Chen, T. Ni, J. Cui, P. Girard, and X. Wen, "Design of a Highly Reliable SRAM Cell with Advanced Self- Recoverability from Soft Errors," Proc. of IEEE Int'l Test Conf. in Asia, Paper C2-1, Taipei, Taiwan, Sep. 2020.
  62. Z. Dou, A. Yan, J. Zhou, Y. Hu, Y. Chen, T. Ni, J. Cui, P. Girard, and X. Wen, "Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors," Proc. of IEEE Int'l Test Conf. in Asia, pp. 35-40, Taipei, Taiwan, Sep. 2020.
  63. A. Yan, Z. Xu, K. Yang, J. Cui, Z. Huang, P. Girard, and X. Wen, "A Novel Low-Cost TMR-without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications," IEEE Trans. on Aerospace and Electronic Systems, Vol. 56, No. 4, pp. 2666-2676, Aug. 2020.
  64. A. Yan, X. Feng, X. Zhao, H. Zhou, J. Cui, Z. Ying, P. Girard, and X. Wen, "HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filtering Latch for Safety-Critical Applications," Proc. of IEEE/ACM Design Automation Conf., Paper 63.2, San Francisco, USA, Jul. 2020.
  65. A. Yan, Y. Chen, X. Feng, Z. Chen, Z. Ying, T. Ni, P. Girard, and X. Wen, "N-1 Errors Interceptive Multiple-Modular-Redundancy Voter Designs for Safety-Critical Applications," Poster at IEEE/ACM Design Automation Conf., San Francisco, USA, Jul. 2020.
  66. A. Yan, Y. Hu, J. Cui, Z. Chen, Z. Huang, T. Ni, P. Girard, and X. Wen, "Information Assurance through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment," IEEE Trans. on Computers, Vol. 69, No. 6, pp. 789-799, Jun. 2020.
  67. A. Yan, X. Feng, Y. Hu, C. Lai, J. Cui, Z. Chen, K. Miyase, and X. Wen, "Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments," IEEE Trans. on Aerospace and Electronic Systems, Vol. 52, No. 2, pp. 1163-1171, Apr. 2020.
  68. A. Yan, Y. Ling, J. Cui, Z. Chen, Z. Huang, J. Song, P. Girard, and X. Wen, "Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells based Multiple-Node-Upset-Tolerant Latch Designs," IEEE Trans. on Circuits and Systems--I: Regular Papers, Vol. 67, No. 3, pp. 879-890, Mar. 2020.
  69. A. Yan, J. Zhou, Y. Hu, J. Cui, Z. Huang, P. Girard, and X. Wen, "Novel Quadruple Cross-Coupled Memory Cell Designs with Protection against Single Event Upsets and Double-Node Upsets," IEEE Access, Vol. 7, No. 1, pp. 176188-176196, Dec. 2019.
  70. A. Yan, Z. Wu, L. Lu, Z. Chen, J. Song, Z. Ying, P. Girard, and X. Wen, "Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications," Proc. of IEEE Asian Test Symp., pp. 43-48, Kolkata, India, Dec. 2019.
  71. A. Yan, Z. Wu, J. Zhou, Y. Hu, Y. Chen, Z. Ying, X. Wen, and P. Girard, "Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications," Proc. of IEEE Asian Test Symp., pp. 55-60, Kolkata, India, Dec. 2019.
  72. A. Yan, Y. Chen, Y. Ling, K. Yang, Z. Wu, and X. Wen, "TNUINC: Triple-Node-Upset-Immune Nano-scale CMOS Latch Design for Aerospace Applications," Poster at IEEE Int'l Conf. on Computer Design, Abu Dhabi, United Arab Emirates, Nov. 2019.
  73. C. M. Fuchs, P. Choux, X. Wen, N. M. Murilloy, G. Furanoz, S. Holst, A. Tavoularisz, S.-K. Lu, and A. Plaat, "A Fault-Tolerant MPSoC for CubeSats," Proc. of IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Paper S4-2, Delft, Netherlands, Oct. 2019.
  74. Z. Song, A. Yan, J. Cui, Z. Chen, X. Li and X. Wen, "A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells," Proc. of IEEE Int'l Test Conf. in Asia, pp. 139-144, Tokyo, Japan, Sep. 2019.
  75. R. Ma, S. Holst, X. Wen, A. Yan, and H. Xu, "STAHL: A Novel Scan-Test-Aware Hardened Latch Design," Proc. of IEEE European Test Symp., Paper 4B-2, Baden Baden, Germany, May 2019.
  76. A. Yan, Y. Hu, J. Song, and X. Wen, "Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications," Proc. of Design, Automation and Test in Europe, pp. 1658-1663, Florence, Italy, Mar. 2019.
  77. A. Yan, Z. Wu, J. Guo, J. Song, and X. Wen, "Novel Double-Node-Upset-Tolerant Memory Cell Designs through Radiation-Hardening-by-Design and Layout," IEEE Trans. on Reliability, Vol. 68, No. 1, pp. 354-363, Mar. 2019.
  78. A. Yan, K. Yang, Z. Huang, J. Zhang, J. Cui, X. Fang, M. Yi, and X. Wen, "A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application," IEEE Trans. on Circuits and Systems II: Express Briefs, Vol. 66, No. 2, pp. 287-291, Feb. 2019.
  79. A. Yan, Y. Ling, J. Cui, Z. Chen, J. Song, and X. Wen, "Novel Multiple-Node-Upset-Tolerant Latch Designs through Radiation-Hardening-by-Design Technique for Nanoscale CMOS Technology," Proc. of China Test Conf., Harbin, China, Aug. 2018. (Best Paper Award)
  80. I. Syafalni, T. Sasao, and X. Wen, "Bit-Flip Errors Detection Using Random Partial Don't-Care Keys for a Soft-Error-Tolerant TCAM," Proc. of Int'l Workshop on Logic and Synthesis, pp. 124-131, San Francisco, USA, Jun. 2018.
  81. I. Syafalni, T. Sasao, and X. Wen, "A Method to Detect Bit Flips in a Soft-Error Resilient TCAM," IEEE Trans. on Computer-Aided Design, Vol. 37, No. 6, pp. 1185-1196, Jun. 2018.
  82. S. Holst, R. Ma, and X. Wen, "The Impact of Production Defects on the Soft-Error Tolerance of Hardened Latches," Proc. of IEEE European Test Symp., Paper 7A-1, Bremen, Germany, May-Jun. 2018.
  83. I. Syafalni, T. Sasao, and X. Wen, "Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM," Proc. of IEEE Computer Society Annual Symp. on VLSI, pp. 679-684, Pittsburgh, USA, Jul. 2016.
  84. I. Syafalni, T. Sasao, and X. Wen, "A Soft-Error Tolerant TCAM for Multiple-Bit Flips Using Partial Don't Care Keys," Proc. of Int'l Workshop on Logic and Synthesis, pp. 11-18, Mountain View, USA, Jun. 2015.
  85. I. Syafalni, T. Sasao, X. Wen, S. Holst, and K. Miyase, "A Soft-Error Tolerant TCAM Using Partial Don’t-Care Keys," Poster at IEEE European Test Symp., Cluj-Napoca, Romania, May 2015.
  86. I. Syafalni, T. Sasao, X. Wen, and S. Holst, "Techniques for Mitigating Soft Errors in TCAMs," Proc. of Int'l Symp. on Dependable Integrated Systems, Fukuoka, Japan, Mar. 2015.
  87. I. Syafalni, T. Sasao, X. Wen, S. Holst, and K. Miyase, "Soft-Error Tolerant TCAMs for High-Reliability Packet Classification," Proc. of IEEE Asia Pacific Conf. on Circuits and Systems, pp. 471-474, Ishigaki Island, Japan, Nov. 2014.