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Power-Aware Testing
  1. S. Shi, S. Holst, and X. Wen, "Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling," Proc. of the 16th IEEE Int`l Symp. on Embedded Milticore/Many-core Systems-on-Chip, Paper A9.2, Dec. 2023.
  2. S. Shi, S. Holst, and X. Wen, "GPU-Accelerated Estimation and Reduction of Peak IR-Drop during Scan Chain Shifting," IEICE Trans. on Fundamentals of Electronics, Communications, and Computer Sciences, Vol. E106-D, No. 10, pp. 1694-1704, Oct. 2023.
  3. S. Shi, S. Holst, and X. Wen, "Estimation and Reduction of Peak IR-Drop in Scan Shift," Proc. of the 10th Int'l Symp. on Applied Engineering and Sciences, Paper S-4-6, Kitakyushu, Japan, Dec. 2022.
  4. X. Wen, "Power-Aware Testing in the Era of IoT," Proc. of IEEE Int'l Conf. on Solid-State and Integrated Circuit Technology, Paper B9.1, Nanjing, P. R. China, Oct. 2022.
  5. T. Utsunomiya, R. Hoshino, K. Miyase, S.-K. Lu, X. Wen, and S. Kajihara, "Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits," Proc. of IEEE Int'l Test Conf. in Asia, Paper A4.2, Taipei, Taiwan, Aug. 2022.
  6. K. Baital, A. Chakrabarti, B. Chatterjee, S. Holst, and X. Wen, "Power and Energy Safe Real-Time Multi-Core Task Scheduling," Proc. of the Int'l VLSI Design & Embedded Systems Conf., Paper 1B.2, Virtual Event, Feb. 2022.
  7. S. Shi, S. Holst, and X. Wen, "GPU-Accelerated Prediction and Targeted Mitigation of IR-Drop Hot-Spots in Scan Testing," Proc. of the 9th Int'l Symp. on Applied Engineering and Sciences, Paper CS21, Serdang, Malaysia, Dec. 2021.
  8. T. Utsunomiya, K. Miyase, R. Hoshino, S.-K. Lu, X. Wen, and S. Kajihara, "Evaluation of Power Consumption with Logic Simulation and Placement Information for At-Speed Testing," Proc. of IEEE Workshop on RTL and High Level Testing, Paper S2.2, Matsuyama, Japan, Nov. 2021.
  9. Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, and J. Qian, "On the Efficacy of Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption," IEICE Trans. on Inf. & Syst., Vol. E104-D, No. 6, pp.816-827, Jun. 2021.
  10. R. Oba, K. Miyase, R. Hoshino, S.-K. Lu, X. Wen, and S. Kajihara, "Probability of Switching Activity to Locate Hotspots in Logic Circuits," Proc. of IEEE Workshop on RTL and High Level Testing, Paper 1.4, Penang, Malaysia, Nov. 2020.
  11. S. Holst, S. Shi, and X. Wen, "Targeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test," Proc. of IEEE Pacific Rim Int'l Symp. on Dependable Computing, pp. 124-129, Kyoto, Japan, Dec. 2019.
  12. K. Miyase, Y. Kawano, S.-K. Lu, X. Wen, and S. Kajihara, "A Static Method for Analyzing Hotspot Distribution on the LSI," Proc. of IEEE Int'l Test Conf. in Asia, pp. 73-78, Tokyo, Japan, Sep. 2019.
  13. X. Wen, "Power-Aware Testing for Low-Power VLSI Circuits," Proc. of IEEE Int'l Conf. on Electron Devices and Solid-State Circuits, Paper S12-1, Xi'an, China, Jun. 2019.
  14. Y. Zhang, X. Wen, S. Holst, K. Miyase, S. Kajihara, H.-J. Wunderlich, and J. Qian, "Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing," Proc. of IEEE Asian Test Symp., pp. 149-154, Hefei, China, Oct. 2018.
  15. T. Kato, S. Wang, Y. Sato, S. Kajihara, and X. Wen, "A Flexible Scan-In Power Control Method in Logic BIST and Its Evaluation with TEG Chips," IEEE Trans. on Emerging Topics in Computing, Vol. 8, No. 3, pp. 591-601, Jul.-Sep. 2017.
  16. K. Miyase, Y. Kawano, X. Wen, and S. Kajihara, "Locating Hot Spot with Justification Techniques in a Layout Design," Proc. of IEEE Workshop on RTL and High Level Testing, Paper S1.2, Taipei, Taiwan, Nov. 2017.
  17. Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, and J. Qian, "Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption," Proc. of IEEE Asian Test Symp., pp. 140-145, Taipei, Taiwan, Nov. 2017.
  18. S. Holst, E. Schneider, H. Kawagoe, M. A. Kochte, K. Miyase, H.-J. Wunderlich, S. Kajihara, and X. Wen, "Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors," Proc. of IEEE Int'l Test Conf., Paper 3.4, Fort Warth, USA, Oct.-Nov. 2017. (Distingushed Papr Recognition)
  19. D. Xiang, X. Wen, and L.-T. Wang, "Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudo-Random Test Pattern Generation and Reseeding," IEEE Trans. on VLSI Systems, Vol. 25, No. 3, pp. 942-953, Mar. 2017.
  20. M. Sauer, J. Jiang, S. Reime, K. Miyase, X. Wen, B. Becker, and I. Polian, "On Optimal Power-Aware Path Sensitization," Proc. of Workshop of Test and Reliability for Circuits and Systems, Mar. 5-7, Germany, 2017.
  21. F. Li, X. Wen, S. Holst, K. Miyase, and S. Kajihara, "Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation," Proc. of Int'l Symp. on Applied Engineering and Sciences, Paper E44, Kita-Kyushu, Japan, Dec. 18, 2016.
  22. F. Li, X. Wen, K. Miyase, S. Holst, and S. Kajihara, "Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation," IEICE Trans. on Fundamentals of Electronics, Communications, and Computer Sciences, Vol. E99-A, No. 12, pp. 2310-2319, Dec. 2016.
  23. S. Eggersgluess, S. Holst, D. Tillex, K. Miyase, and X. Wen, "Formal Test Point Insertion for Region-Based Low-Capture-Power Compact At-Speed Scan Test," Proc. of IEEE Asian Test Symp., pp. 173-178, Hiroshima, Japan, Nov. 2016. (ATS 30th Anniversary Compendium Paper)
  24. S. Holst, E. Schneider, X. Wen, S. Kajihara, Y. Yamato, H.-J. Wunderlich, and M. A. Kochte, "Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test," Proc. of IEEE Asian Test Symp., pp. 19-24, Hiroshima, Japan, Nov. 2016.
  25. M. Sauer, J. Jiang, S. Reimer, K. Miyase, X. Wen, B. Becker, and I. Polian, "On Optimal Power-Aware Path Sensitization," Proc. of IEEE Asian Test Symp., pp. 179-184, Hiroshima, Japan, Nov. 2016. (ATS 30th Anniversary Compendium Paper)
  26. T. Kato, S. Wang, Y. Sato, S. Kajiahara, and X. Wen, "A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST," Proc. of IEEE Asian Test Symp., pp. 203-208, Hiroshima, Japan, Nov. 2016.
  27. T. Chen, D. Shen, X. Yi, H. Liang, X. Wen, and W. Wang, "Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures," IEICE Trans. on Inf. & Syst., Vol. E99-D, No. 11, pp. 2672-2681, Nov. 2016.
  28. X. Wen, "Power-Aware Testing For Low-Power VLSI Circuits," Proc. of IEEE Int'l Conf. on Solid-State and Integrated Circuit Technology, Paper S37-1, Hangzhou, China, Oct. 2016.
  29. S. Eggersgluess, K. Miyase, and X. Wen, "SAT-Based Post-Processing for Regional Capture Power Reduction in At-Speed Scan Test Generation," Proc. of IEEE European Test Symp., Paper 7A.1, Amsterdam, The Netherlands, May 2016.
  30. D. Xiang, K. Shen, B. B. Bhattacharya, X. Wen, and X. Lin, "Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill," IEEE Trans. on Computer-Aided Design, Vol. 35, No. 3, pp. 499-512, Mar. 2016.
  31. W.-S. Ding, H.-Y. Hsieh, C.-Y. Han, C.-M. Li, and X. Wen, "Test Pattern Modification for Average IR-Drop Reduction," IEEE Trans. on VLSI Systems, Vol. 24, No. 1, pp. 38-49, Jan. 2016.
  32. K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. A. Kochte, E. Schneider, H.-J. Wunderlich, and J. Qian, "Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch," Proc. of IEEE Asian Test Symp., pp. 103-108, Bombay, India, Nov. 2015. (Best Paper Award) (ATS 30th Anniversary Compendium Paper)
  33. X. Wen, "Power Supply Noise and Its Reduction in At-Speed Scan Testing," Proc. of IEEE Int'l Conf. on ASIC, Paper B5-3, Chengdu, China, Nov. 5, 2015.
  34. K. Miyase, M. Sauer, B. Becker, X. Wen, and S. Kajihara, "Identification of High Power Consuming Areas with Gate Type and Logic Level Information," Proc. of IEEE European Test Symp., Paper 9.1, Cluj-Napoca, Romania, May 2015.
  35. A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, and L.-T. Wang, "On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST," IEICE Trans. on Inf. & Syst., Vol. E97-D, No. 10, pp. 2706-2718, Oct. 2014.
  36. A. Tomita, X. Wen, Y. Sato, S. Kajihara, K. Miyase, S. Holst, P. Girard, M. Tehranipoor, and L.-T. Wang, "On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST," Proc. of IEEE Asian Test Symp., pp.19-24, Yilan, Taiwan, Nov. 2013.
  37. K. Miyase, M. Sauer, B. Becker, X. Wen, and S. Kajihara, "Search Space Reduction for Low-Power Test Generation," Proc. of IEEE Asian Test Symp., pp.171-176, Yilan, Taiwan, Nov. 2013.
  38. C.-M. Li, W.-S. Ding, H.-Y. Hsieh, and X. Wen, "Test Pattern Modification for Average IR-Drop Reduction," Poster at IEEE Int'l. Test Conf., Anaheim, USA, Sep. 2013.
  39. Y. Yamato, X. Wen, M. A. Kochte, K. Miyase, S. Kajihara, and L.-T. Wang, "LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing", IEEE Design & Test of Computers, Vol. 30, No. 4, pp. 60-70, Aug. 2013.
  40. Y.-T. Lin, J.-L. Huang, and X. Wen, "SafeTIDE: A Technique for Transition Isolation Scan Cells Hardware Overhead Reduction," Proc. of VLSI Test Technology Workshop, Paper 4.4, New Taipei, Taiwan, Jul. 2013.
  41. K. Miyase, R. Sakai, X. Wen, M. Aso, H. Furukawa, Y. Yamato, and S. Kajihara, "A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing", IEICE Trans. on Inf. & Syst., Vol. E96-D, No. 9, pp. 2003-2011, Sep. 2013.
  42. K. Miyase, M. Sauer, B. Becker, X. Wen, and S. Kajihara, "Controllability Analysis of Local Switching Activity for Layout Design," Proc. of Workshop on Design and Test Methodologies for Emerging Technologies, Paper 2, Avignon, France, May 2013.
  43. K. Enokimoto, X. Wen, K. Miyase, J.-L. Huang, S. Kajihara, and L.-T. Wang, "On Guaranteeing Capture Safety in At-Speed Scan Testing With Broadcast-Scan-Based Test Compression," Proc. of IEEE Int'l Conf. on VLSI Design, pp. 279-284, Pune, India, Jan. 2013.
  44. Y.-T. Lin, J.-L Huang, and X. Wen, "A Transition Isolation Scan Cell Design for Low Shift and Capture Power," Proc. of IEEE Asian Test Symp., pp. 107-112, Niigata, Japan, Nov. 2012.
  45. X. Wen, Y. Nishida, K. Miyase, S. Kajihara, P. Girard, M. Tehranipoor, and L.-T. Wang, "On Pinpoint Capture Power Management in At-Speed Scan Test Generation," Proc. of IEEE Int'l Test Conf., Paper 6.1, Anaheim, USA, Nov. 2012. (2nd-Ranked Submission)
  46. Y.-T. Lin, J.-L. Huang, and X. Wen, "A Transition Isolation Scan Cell Design for Low Shift and Capture Power," Proc. of VLSI Test Technology Workshop, Yilan, Taiwan, Paper 2.2, Jul. 2012.
  47. X. Wen, "Power-Aware Testing: The Next Stage", Proc. of IEEE European Test Symp., Annecy, France, May, 2012.
  48. K. Miyase, M. Aso, R. Ootsuka, X. Wen, H. Furukawa, Y. Yamato, K. Enokimoto, and S. Kajihara, "A Novel Capture-Safety Checking Method for Multi-Clock Designs and Accuracy Evaluation with Delay Capture Circuits," Proc. of IEEE VLSI Test Symp., pp. 197-202, Hawaii, USA, Apr. 2012.
  49. H. Salmani, W. Zhao, M. Tehranipoor, S. Chakravarty, P. Girard, and X. Wen, "Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns," ASP Journal of Lower Power Electronics, Vol. 8, No. 2, pp. 248-258, Apr. 2012.
  50. K. Miyase, H. Tanaka, K. Enokimoto, X. Wen, and S. Kajihara, "Additional Path Delay Fault Detection with Adaptive Test Data," Proc. of IEEE Workshop on RTL and High Level Testing, pp. 31-34, Jaipur, India, Nov. 2011.
  51. K. Miyase, U. Uchinodan, K. Enokimoto, Y. Yamato, X. Wen, S. Kajihara, F. Wu, L. Dilillo, A. Bosio, and P. Girard, "Effective Launch Power Reduction for Launch-Off-Shift Scheme with Adjacent-Probability-Based X-Filling," Proc. of IEEE Asian Test Symp., pp. 90-95, New Delhi, India, Nov. 2011.
  52. A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, K. Miyase, and X. Wen, "Power-Aware Test Pattern Generation for At-Speed LOS Testing," Proc. of IEEE Asian Test Symp., pp. 506-510, New Delhi, India, Nov. 2011.
  53. X. Wen, "Towards the Next Generation of Low-Power Test Technologies," Proc. of IEEE Int'l Conf. on ASIC, Paper 1E-1, Amoi, China, Oct. 2011.
  54. Y. Yamato, X. Wen, M. A. Kochte, K. Miyase, S. Kajihara, and L.-T. Wang, "A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failure in Scan Testing," Proc. of IEEE Int'l Test Conf., Paper 12.1, Anaheim, USA, Sep. 2011. (8th-Ranked Submission)
  55. Y.-T. Lin, J.-L. Huang, and X. Wen, "Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing", Proc. of IEEE Int'l Test Conf., Paper 2.3, Anaheim, USA, Sep. 2011.
  56. M. A. Kochte, K. Miyase, X. Wen, S. Kajihara, Y. Yamato, K. Enokimoto, and H.-J. Wunderlich, "SAT-Based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures," Proc. of IEEE Int'l Symp. on Low Power Electronics and Design, pp. 33-38, Fukuoka, Japan, Aug. 2011.
  57. X. Wen, "VLSI Testing and Test Power," Proc. of Workshop on Low Power System on Chip (SoC), Paper 4.1, Orlando, USA, Jul. 2011.
  58. K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, H. Furukawa, X. Wen, and S. Kajihara, "Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing," IEICE Trans. on Inf. & Syst., Vol.E94-D, No.6, pp.1216-1226, Jun. 2011.
  59. F. Wu, L. Dilillo, A. Bosio, P. Girard, M. Tehranipoor, K. Miyase, X. Wen, and N. Ahmed, "Mapping Test Power to Functional Power Through Smart X-Filling for LOS Scheme," Proc. of IEEE Int'l Workshop on Impact of Low-Power Design on Test and Reliability., 4 pages, Trondheim, Norway, May 2011.
  60. H. Salmani, W. Zhao, M. Tehranipoor, S. Chacravarty, P. Girard, and X. Wen, "Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns," Proc. of IEEE Int'l Workshop on Impact of Low-Power design on Test and Reliability, 4 pages, Trondheim, Norway, May 2011.
  61. X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. Kochte, S. Kajihara, P. Girard, and M. Tehranipoor, "Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing," Proc. of IEEE VLSI Test Symp., pp. 166-171, Dana Point, USA, May 2011.
  62. F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, and N. Ahmed, "Power Reduction Through X-Filling of Transition Fault Test Vectors for LOS Testing," Proc. of IEEE Int'l Conf. on Design & Technology of Integrated Systems in Nanoscale Era, pp. 1-6, Athens, Greece, Apr. 2011.
  63. Y. Yamato, X. Wen, K. Miyase, H. Furukawa, and S. Kajihara, "A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing," IEICE Trans. on Inf. & Syst., Vol.E94-D, No.4, pp. 833-840, Apr. 2011.
  64. K. Miyase, X. Wen, M. Aso, H, Furukawa, Y. Yamato, and S. Kajihara, "Transition-Time-Relation Based Capture-Safety Checking for At-Speed Scan Test Generation," Proc. of Design Automation, and Test in Europe, pp. 895-898, Grenoble, France, Mar. 2011.
  65. K. Miyase, M. A. Kochte, X. Wen, S. Kajihara, and H.-J. Wunderlich, "Low-Capture-Power Post-Processing Test Vectors for Test Compression Using SAT Solver," Proc. of IEEE Workshop on Defect and Date Driven Testing, 4 pages, Austin, USA, Nov. 2010.
  66. F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, and N. Ahmed, "Is Test Power Reduction Through X-Filling Good Enough?," Proc. of IEEE Int'l Test Conf., p. 805, Austin, USA, Nov. 2010.
  67. X. Wen, "Low-Power Test for Low-Power Devices," Proc. of IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI and nanotechnology Systems, p. 261, Kyoto, Japan, Oct. 2010.
  68. F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, X. Wen, and N. Ahmed, "A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for LOS and LOC Schemes," ASP Journal of Lower Power Electronics, Vol. 6, No. 2, pp. 359-374, Aug. 2010.
  69. K. Miyase, X. Wen, S. Kajihara, Y. Yamato, A. Takashima, H. Furukawa, K. Noda, H. Ito, K. Hatayama, T. Aikyo, and K. K. Saluja, "A Study of Capture-Safe Test Generation Flow for At-Speed Testing," IEICE Trans. on Fundamentals of Electronics, Communications, and Computer Sciences, Vol. E93-A, No. 7, pp. 1309-1318, Jul. 2010.
  70. F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, J. Ma, W. Zhao, and X. Wen, "Analysis of Power Consumption and Transition Fault Coverage for LOS and LOC Testing Schemes," Proc. of IEEE Int'l Symp. on Design and Diagnostics of Electronic Circuits and Systems, pp. 376-381, Vienna, Austria, Apr. 2010.
  71. X. Wen, K. Enokimoto, K. Miyase, S. Kajihara, M. Aso, and H. Furukawa, "CAT (Critical-Area-Targeted): A New Paradigm for Reducing Yield Loss Risk in At-Speed Scan Testing," Proc. of Symp. II (ISTC/CSTIC): Metrology, Reliability and Testing, pp. 197-202, Shanghai, China, Mar., 2010.
  72. K. Miyase, X. Wen, H. Furukawa, Y. Yamato, S. Kajihara, P. Girard, L.-T. Wang, and M. Tehranipoor, "High Launch Switching Activity Reduction in At-Speed Scan Testing using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme," IEICE Trans. on Inf. & Syst., Vol. E93-D,No. 1, pp. 2-9, Jan. 2010.
  73. M.-F. Wu, J.-L. Huang, X. Wen, and K. Miyase, "Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 11, pp. 1767-1776, Nov. 2009.
  74. I. Beppu, K. Miyase, Y. Yamato, X. Wen, and S. Kajihara, "X-Identification According to Required Distribution for Industrial Circuits," Proc. of IEEE Workshop on RTL and High Level Testing, pp. 76-81, Hong Kong, Nov. 2009.
  75. K. Enokimoto, X. Wen, Y. Yamato, K. Miyase, H. Sone, S. Kajihara, M. Aso, and H. Furukawa, "CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing," Proc. of IEEE Asian Test Symp., pp. 99-104, Taichung, Taiwan, Nov. 2009.
  76. Y. Yamato, X. Wen, K. Miyase, H. Furukawa, and S. Kajihara, "A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing," Proc. of IEEE Pacific Rim Int'l Symp. on Dependable Computing, pp. 81-86, Shanghai, China, Nov. 2009.
  77. I. Beppu, K. Miyase, Y. Yamato, X. Wen, and S. Kajihara, "Optimizing the Percentage of X-Bits to Reduce Switching Activity," Proc. of IEEE Workshop on Defect and Date Driven Testing, 4 pages, Austin, USA, Nov., 2009.
  78. K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, X. Wen, and S. Kajihara, "A Novel Post-ATPG IR-Drop Reduction Scheme for At-Speed Scan Testing in Broadcast-Scan-Based Test Compression Environment," Proc. of IEEE/ACM Int'l Conf. on Computer Aided Design, pp. 97-104, San Jose, USA, Nov. 2009.
  79. 温暁青, "シグナルインテグリティ考慮型LSIテストを目指して," 信頼性学会誌, Vol. 31, No. 7, pp. 498-505, 2009年10月.
  80. Y. Yamatoa, X. Wen, K. Miyase, H. Furukawa, and S. Kajihara, "Power-Aware Test Generation for Reducing Yield Loss Risk in At-Speed Scan Testing," Proc. of Symp. II (ISTC/CSTIC): Metrology, Reliability and Testing, pp. 231-236, Shanghai, China, Mar. 2009.
  81. H. Furukawa, X. Wen, K. Miyase, Y. Yamato, S. Kajihara, Patrick Girard, L.-T. Wang, and M. Tehranipoor, "CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing," Proc. of IEEE Asian Test Symp., pp. 397-402, Sapporo, Japan, Nov. 2008.
  82. K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, H. Furukawa, X. Wen, and S. Kajihara, "Effective IR-Drop Reduction in At-Speed Scan Testing Using Distribution-Controlling X-Identification," Proc. of IEEE/ACM Int'l Conf. on Computer Aided Design, pp. 52-58, San Jose, USA, Nov. 2008.
  83. J. Ma, J. Lee, M. Tehranipoor, X. Wen, and A. Crouch, "Identification of IR-Drop Hot-Spots in Defective Power Distribution Network Using TDF ATPG," Proc. of IEEE Workshop on Defect and Data Driven Testing, 7 pages, Santa Clara, USA, Oct. 2008.
  84. Y. Yamato, X. Wen, K. Miyase, H. Furukawa, and S. Kajihara, "GA-Based X-Filling for Reducing Launch Switching Activity in At-Speed Scan Testing," Proc. of IEEE Workshop on Defect and Date Driven Testing, 4 pages, Santa Clara, USA, Oct. 2008.
  85. M.-F. Wu, J.-L. Huang, X. Wen, and K. Miyase, "Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing," Proc. of IEEE Int'l Test Conf., Paper 13.1, Santa Clara, USA, Oct. 2008. (Report)
  86. C. P. Ravikumar, M. Hirech, and X. Wen, "Test Strategies for Low-Power Devices," ASP Journal of Low Power Electronics, Vol. 4, No.2, pp. 127-138, Aug. 2008.
  87. X. Wen, K. Miyase, S. Kajihara, H. Furukawa, Y. Yamato, A. Takashima, K. Noda, H. Ito, K. Hatayama, T. Aikyo, and K. K. Saluja, "A Capture-Safe Test Generation Scheme for At-Speed Scan Testing," Proc. of IEEE European Test Symp., pp. 55-60, Verbania, Italy, May 2008.
  88. 李华伟, 温晓青, 向东, 徐强, 王智弘, 李昂, "VLSI/SOC测试中的功耗主题—挑战性问题和现有解决方法," 第五届中国测试学术会议论文集, 苏州, 中国, 2008年5月.
  89. C. P. Ravikumar, M. Hirech, and X. Wen, "Test Strategies for Low-Power Devices," Proc. of Design Automation, and Test in Europe, pp. 728-733, Munich, Germany, Mar. 2008.
  90. X. Wen, K. Miyase, T. Suzuki, S. Kajihara, L.-T. Wang, K. K. Saluja, and K. Kinoshita, "Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing," Journal of Electronic Testing: Theory and Applications, Special Issue on Low Power Testing, Vol. 24, No. 4, pp.379-391, Jan. 2008.
  91. X. Wen, K. Miyase, S. Kajihara, T. Suzuki, Y. Yamato, P. Girard, Y. Ohsumi, and L.-T. Wang, "A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing," Proc. of IEEE Int'l Test Conf., Paper 25.1, Santa Clara, USA, Oct. 2007.
  92. X. Wen, S. Kajihara, K. Miyase, T. Suzuki, K. K. Saluja, L.-T. Wang, and K. Kinoshita, "A Novel ATPG Method for Capture Power Reduction During Scan Testing," IEICE Trans. on Inf. & Syst., Vol. E90-D, No. 9, pp. 1398-1405, Sep. 2007. (Best Paper Award)
  93. X. Wen, K. Miyase, T. Suzuki, S. Kajihara, Y. Ohsumi, and K. K. Saluja, "Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing," Proc. of IEEE/ACM Design Automation Conf., pp. 527-532, San Diego, USA, Jun. 2007.
  94. X. Wen, K. Miyase, T. Suzuki, Y. Yamato, S. Kajihara, L.-T. Wang, and K. K. Saluja, "A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation," Proc. of IEEE Int'l Conf. on Computer Design, pp. 251-258, San Jose, USA, Oct. 2006.
  95. Y. Hu, Y. Han, X. Li, H. Li, and X. Wen, "Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time," IEICE Trans. on Inf. & Syst., Vol. E89-D, No. 10, pp. 2616-2625, Oct. 2006.
  96. X. Wen, Y. Yamashita, S. Kajihara, L.-T. Wang, K. K. Saluja, and K. Kinoshita, "A New Method for Low-Capture-Power Test Generation for Scan Testing", IEICE Trans. on Inf. & Syst., Vol. E89-D, No. 5, pp. 1679-1686, May 2006. (Best Paper Award)
  97. X. Wen, S. Kajihara, K. Miyase, T. Suzuki, K. K. Saluja, L.-T. Wang, K. S. Abdel-Hafez, and K. Kinoshita, "A New ATPG Method for Efficient Capture Power Reduction During Scan Testing," Proc. of IEEE VLSI Test Symp., pp. 58-63, Berkeley, USA, Apr.-May 2006.
  98. X. Wen, T. Suzuki, S. Kajihara, K. Miyase, Y. Minamoto, L.-T. Wang, and K. K. Saluja, "Efficient Test Set Modification for Capture Power Reduction," ASP Journal of Low Power Electronics, Vol. 1, No. 3, pp. 319-330, Dec. 2005.
  99. X. Wen, Y. Yamashita, S. Morishima, S. Kajihara, L.-T. Wang, K. K. Saluja, and K. Kinoshita, "Low-Capture-Power Test Generation for Scan-Based At-Speed Testing," Proc. of IEEE Int'l Test Conf., Paper. 39.2, Austin, USA, Nov. 2005.
  100. Y. Hu, Y. Han, X. Li, H. Li, and X. Wen, "Compression/Scan Co-Design for Reducing Test Data Volume, Scan-In Power Dissipation and Test Application Time," Proc. of IEEE Pacific Rim Int'l Symp. on Dependable Computing, p. 8, Changsha, China, Dec. 2005.
  101. Y. Han, Y. Hu, X. Li, H. Li, A. Chandra, and X. Wen, "Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores," IEICE Trans. on Inf. & Syst., Vol. E88-D, No. 9, pp. 2126-2134, Sept. 2005.
  102. X. Wen, Y. Yamashita, S. Morishima, S. Kajihara, L.-T. Wang, K. K. Saluja, and K. Kinoshita, "A Method for Low-Capture-Power At-Speed Test Generation," Proc. of IEEE Workshop on RTL and High Level Testing, pp. 40-49, Harbin, China, Jul. 2005.
  103. X. Wen, Y. Yamashita, S. Kajihara, L.-T. Wang, K. K. Saluja, and K. Kinoshita, "On Low-Capture-Power Test Generation for Scan Testing," Proc. of IEEE VLSI Test Symp., pp. 265-270, Palm Springs, USA, May 2005.